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ir3827 1 www.irf.com ? 20 13 international rectifier july 18, 2013 6a highly integrated sup ir buck tm single - input voltage, synchronous buck regulator features description ? sin gle input voltage range from 5 v to 21v ? wide i nput v oltage r ange from 1.0v to 21v with external v cc bias voltage ? output v oltag e r ange from 0.6v to 0.86 % pvin ? enhanced l ine /load r egulation with feedf orward ? programmable s witching f requency up to 1.2mhz ? t hree user selectable soft - start time ? user selectable ldo o utput voltage ? enable input with v oltage m onitoring c apability ? thermally c ompensated c urrent l imit with robust hiccup mode over current protection ? synchronization to an e xternal c lock ? enhanced p re - b ias s tart - u p ? precis e r eference v oltage (0.6v+/ - 0. 6 %) ? open - d rain pgood i ndication ? optional power up sequencing ? integrated mosfet drivers and b ootstrap d iode ? the rmal shut down ? monotonic start - up ? operating temp: - 40 c < t j < 125 c ? package s ize: 4mm x 5mm pqfn ? lead - free, halogen - free and rohs 6 compliant the ir3827 supirbuck tm is an easy - to - use, fully integrated and highly efficient dc/dc regulator. the onboard pwm controller and mosfets make ir3827 a space - efficient solution, providing accurate power delivery for low output voltage applications. ir3827 is a versatile regulator which offers programmable switching frequency and internally set current limit while o perating in wide range of input and output voltage conditions. the switching frequency is programmable from 300khz to 1.2mhz for an optimum solution. it also features important protection functions, such as pre - bias startup, thermally compensated current l imit, over voltage protection and thermal shutdown to give required system level security in the event of fault conditions. applications ? computing applications ? set top box applications ? storage applications ? data center applications ? distributed point of load power architectures ordering information base part number package type standard pack orderable part number form quantity ir3827 pqfn 4 mm x 5 mm tape and reel 750 ir3827mtr1pbf ir3827 pqfn 4 mm x 5 mm tape and reel 4000 ir3827mtrpbf ir3 827 ? ? ? ? ? ? pbf ? lead free tr /tr1 ? tape and reel m ? p q fn package
ir3827 2 www.irf.com ? 20 13 international rectifier july 18, 2013 basic application boot vcc/ ldo _out fb comp gnd pgnd sw pgood rt/sync pvin vin enable ir3827 ss _select vin pgood vo ldo _select seq figure 1 ir38 2 7 basic application circuit figure 2 ir3827 efficiency pinout diagram ir3827 13 12 11 17 14 15 16 1 2 3 4 5 6 8 9 10 fb ss_ select comp gnd rt/sync pgood ldo_ select vin vcc/ldo_out pgnd pvin boot enable sw gnd seq 7 n /c figure 3 4mm x 5mm pqfn (top view)
ir3827 3 www.irf.com ? 20 13 international rectifier july 18, 2013 block diagram seq fb rt/sync sw pgnd enable vcc oc tsd hdin uvcc uven hdrv ldrv vin ssok 0.6v vref seq por por uvcc gnd oc ov ov vin ss_select fb ldo_select vcc / ldo _ out 5.1v/6.9v internal ldo uvcc thermal shut down fault control + - + + e / a c omp vref + - control logic 0.15v soft start uven por over voltage fault por vref intl_ss por gate drive pv in ldin b oot vcc por fault over current protection pg ood figure 4 simplified b lock d iagram
ir3827 4 www.irf.com ? 20 13 international rectifier july 18, 2013 pin descriptions pin # pin name pin description 1 fb inverting input to the error amplifier. this pin is connected directly to the output of the regulator via a resistor divider to set the output voltage and to provide the feedback signal to the error amplifier. 2 n/c should not be connected to other signals on pcb layout. it is internal ly connected for test ing purpose. 3 comp output of error amplifier. an external resistor and capacitor network is typically connected from this pin to fb pin to form a loop compensator . 4 , 17 gnd signal ground for internal reference and control circuitry. 5 rt/sync multi - function pin to set the switching frequency. the internal oscillator frequency is set with a resistor between this pin and gnd. or synchronization to an external clock by connecting this pin to the external clock signal through a diode. 6 ss_select soft start selection pin. three user selectable soft start time is available: 1.5ms (ss_select=vcc), 3ms (ss_select=float), 6ms (ss_select=gnd) 7 pgood open - drain power good indication pin. connect a pull - up resistor from this pin to vcc. 8 ldo_select ldo output voltage selection pin. float gives 5.1v and low 0v (gnd) gives 6.9v 9 v in input for i nternal ldo. a 1.0f capacitor should be connected between this pin and pgnd. if external supply is connected to vcc/ldo_out pin, this pin should be shorted to vcc/ ldo_out pin. connecting this pin to pv in can also implement the input voltage feedforward. 10 vcc/ldo_out output of the internal ldo and optional input of an external biased supply voltage. a minimum 2.2f ceramic capacitor is recommended between this pin and pgnd. 11 pgnd power ground. this pin serves as a separated ground for the mosfet drivers and should be connected to the system?s power ground plane. 12 sw switch node. c onnected this pin to the output inductor. 13 pv in input voltage for power stage. 14 boot supply voltage for high side driver, a 100nf capacitor should be connected between this pin and sw pin. 15 enable enable pi n to turn on and off the device. i nput voltage monitoring (input uvlo ) can also be implemented by connecting this pin to pvin pin through a resistor divider. 16 seq sequence pin to do simultaneous and ratiometric sequencing operation. a resistor divider can be connected from master output to this pin for sequencing mode of operation. if not used, leave it open. 17 gnd signal ground for internal reference and control circuitry.
ir3827 5 www.irf.com ? 20 13 international rectifier july 18, 2013 absolute maximum rat ings stresses beyond th e se listed under ?absolute maximum ratings? may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications are not implied. pvin, vin to pgnd (note 4 ) - 0.3v to 25v vcc/ldo_out to pgnd (note 4 ) - 0.3v to 8v (note 1 ) boot to pgnd (note 4 ) - 0.3v to 33v sw to pgnd (note 4 ) - 0.3v to 25v (dc), - 4v to 25v (ac, 100ns) boot to sw - 0.3v to v cc + 0.3v (note 2) pgood, ss_select to gnd (note 4 ) - 0.3v to v cc + 0.3v (note 2) other input/output pins to gnd (note 4 ) - 0.3v to +3.9v pgnd to gnd - 0.3v to +0.3v thermal information junction to ambient thermal resistance ? ja 32 c/w (note 3) junction to pcb thermal resistance ? j - pcb 2 c/w storage temperature range - 55c to 150c junction temperature range - 40c to 150c note 1: vcc must not exceed 7.5v for junction temperature between - 10c and - 40c note 2: must not exceed 8v note 3: based on irdc3827 demo board - 2.6x2.2, 4 - layer pcb board using 2 oz. copper on each layer. note 4: pgnd pin and gnd pin are connected together.
ir3827 6 www.irf.com ? 20 13 international rectifier july 18, 2013 electrical specifica tions recommended operatin g conditions symbol min max unit s input voltage range with external vcc note 5 , note 7 pv in 1.0 21 v input voltage range with internal ldo note 6 , note 7 v in , pv in 5.5 21 supply voltage range ( note 6) v cc 4.5 7.5 supply voltage range ( note 6) boot to sw 4.5 7.5 output voltage range v 0 0.6 0.86 x pv in output current range i 0 0 6 a switching frequency f s 300 1200 khz operating junction temperature t j -40 125 c note 5: v in is connected to v cc to bypass the internal ldo. note 6: v in is connected to pv in . for single - rail applications with pv in =v in = 4.5v - 5.5v, please refer to the application information in the section of user selectable internal ldo and the section of over current protection . note 7: maximum sw node voltage should not exceed 25v. elect rical characteristic s unless otherwise specified, these specifications apply over, 5.5v < v in = pv in < 21v, 0c < t j < 125c, ldo_select=gnd, ss_select= f loat. typical values are specified at t a = 25c. parameter symbol conditions min typ max units power stage power losses p loss pv in = v in = 12v, v o =1.2v, i o = 6a, f s =600khz, l =1 .0 uh, ldo_select=gnd. note 8 1.1 w pv in = v in =12v, v o =1.2v, i o =6a, f s =600khz, l=1 .0 uh, ldo_select=float. note 8 1.3 top switch r ds(on) r ds (on) - t v b oot - vsw=5.1v,i o = 6a, t j = 25c 21 29 m? v b oot - vsw=6.9v,i o = 6a, t j = 25c 16 22 bottom switch r ds(on) r ds (on) - b v cc = 5.1v, i o = 6a, t j = 25c 21.4 30 v cc = 6.9v, i o = 6a, t j = 25c 16.8 23 bootstrap diode forward voltage v d i(boot) = 10ma 180 260 470 mv sw leakage current v sw = 0v, enable = 0v 1 a v sw = 0v, enable = high, v seq =0v 1 a dead band time t d note 8 10 ns
ir3827 7 www.irf.com ? 20 13 international rectifier july 18, 2013 electrical character istics (continued) unless otherwise specified, these specifications apply over, 5.5v < v in = pv in < 21v, 0c < t j < 125c, ldo_select=gnd, ss_select= f loat. typical values are specified at t a = 25c. parameter symbol conditions min typ max units supply current vin supply current (standby) i in(standby) en = low, no switching 200 a vin supply current (dynamic) i in(dyn) en = high, f s = 600khz, v in = pv in = 21v, ldo_select=gnd 10 13 ma en = high, f s = 600khz, v in = pv in = 21v, ldo_select=float 8 11 v cc /ldo_out output voltage v cc v in(min) = 5.5v, i o = 0 - 30ma, cload =2.2uf, ldo_select=float 4.75 5.1 5.4 v v in(min) = 7.3v, i o = 0 - 30ma, cload = 2.2uf, ldo_select=gnd 6.5 6.9 7.2 ldo_select input bias c urrent ldo_select=gnd 30 60 ua ldo dropout voltage v cc_drop v in =6.5v,i o =30ma, cload=2.2uf , ldo_select=gnd 0.7 v v in =4.7v,io=25ma, cload=2.2uf , ldo_select=float 0.7 short circuit current i short ldo_select=gnd 70 ma oscillator rt voltage v rt 1.0 v frequency range f s rt = 80.6k ? 270 300 330 khz rt = 39.2k ? 540 600 660 rt = 19.1k ? 1080 1200 1320 ramp amplitude v ramp v in = 7.3v, vin slew rate max = 1v/s, note 8 1.095 v p - p v in = 12v, vin slew rate max = 1v/s, note 8 1.80 v in = 21v, vin slew rate max = 1v/s, note 8 3.15 v in =v cc =5v, for external v cc operation, note 8 0.75
ir3827 8 www.irf.com ? 20 13 international rectifier july 18, 2013 electrical character istics (continued) unless otherwise specified, these specifications apply over, 5.5v < v in = pv in < 21v, 0c < t j < 125c, ldo_select=gnd, ss_select= f loat. typical values are specified at t a = 25c. parameter symbol conditions min typ max units ramp offset note 8 0.16 v minimum pulse width t min(ctrl) note 8 60 ns maximum duty cycle d max f s = 300khz, v in =p v in = 12v 86 % fixed off time t off note 8 200 250 ns sync frequency range f sync 270 1320 khz sync pulse duration t sync 100 200 ns sync level threshold high 3 v low 0.6 error amplifier input offset voltage v fb ? v seq , v seq =0.3v -3 + 3 % input bias current (v fb ) i f b (e/a) -1 +1 a input bias current (v seq ) i s eq (e/a) 0 +4 sink current i sink (e/a) 0.4 0.85 1.2 ma source current i source (e/a) 4 7.5 11 ma slew rate sr note 8 7 12 20 v/s gain - bandwidth product gbwp note 8 20 30 40 mhz dc gain gain note 8 100 110 120 db maximum output voltage v max (e/a) 1.7 2.0 2.3 v minimum output voltage v min (e/a) 100 mv common mode input voltage 0 1.2 v reference voltage (v ref ) feedback voltage v fb ldo_select = gnd 0.6 v ldo_select = float 0.6 accuracy 0c < t j < 70c - 0.6 +0.6 % - 40c < t j < 1 2 5c ; note 9 -1. 2 +1. 2 soft start soft start ramp rate ss_select=high 0.34 0.4 0.46 mv/s ss_select=float 0.17 0.2 0.23 ss_select= gnd 0.085 0.1 0.115 ss_select i nput b ias c urrent ldo_select=gnd ss_select= gnd 40 80 ua
ir3827 9 www.irf.com ? 20 13 international rectifier july 18, 2013 electrical character istics (continued) unless otherwise specified, these specifications apply over, 5.5v < v in = pv in < 21v, 0c < t j < 125c, ldo_select=gnd, ss_select= f loat. typical values are specified at t a = 25c. parameter symbol conditions min typ max units power good power good turn on threshold vpg (on) v fb rising 85 90 95 % v ref power good lower turn off threshold vpg (lower) v fb falling 80 85 90 % v ref power good turn on delay tpg (on)_d v fb r ising, s ee vpg (on) 2.56 ms power good upper turn off threshold vpg (upper) v fb r ising 115 120 125 % v ref pgood comparator delay v fb < vpg (lower) or v fb > vpg (upper) 1 2 3.5 s pgood voltage low pg(voltage) i p g ood = - 5ma 0.5 v under - voltage lockout v cc - start threshold v cc uvlo start v cc r ising t rip level 3.9 4.1 4.3 v v cc - stop threshold v cc uvlo stop vcc f alling t rip level 3.6 3.8 4.0 v enable - start - threshold enable uvlo start ramping up 1.14 1.2 1.26 v enable - stop - threshold enable uvlo stop ramping down 0.95 1 1.05 enable leakage current i en _lk enable = 3.3v 1 a over - voltage protection ovp trip threshold ovp_v th v fb r ising 115 120 125 % v ref ovp comparator delay t ovp_d 1 2 3.5 s over - current protection current limit i limit t j = 25c, ldo_select=float 6.2 7.3 8.5 a t j = 25c, ldo_select=gnd 7.9 9.3 10.8 hiccup blanking time t blk _hiccup ss_select = vcc, note 8 10 ms ss_select = float, note 8 20 ss_select = gnd, note 8 40
ir3827 10 www.irf.com ? 20 13 international rectifier july 18, 2013 electrical character istics (continued) unless otherwise specified, these specifications apply over, 5.5v < v in = pv in < 21v, 0c < t j < 125c, ldo_select=gnd, ss_select=float. typical values are specified at t a = 25c. parameter symbol conditions min typ max units upper gate driver source resistance v b oot -v sw = 5.1v, note 8 3 sink resistance v b oot -v sw = 5.1v, note 8 4 lower gate driver source resistance v cc = 5.1v, note 8 2 sink resistance v cc = 5.1v, note 8 0.8 over - temperature protection thermal shutdown threshold note 8 145 c hysteresis note 8 20 note 8: guaranteed by design , but not tested in production . note 9: cold temperature performance is guaranteed via correlation using statistical quality control. not tested in production.
ir3827 11 www.irf.com ? 20 13 international rectifier july 18, 2013 typical efficiency a nd power loss curves pv in = 12v, v cc = internal ldo, ldo_select = float, i o = 0a - 6a, f s = 600 khz, room temperature, no air flow. note that the efficiency and power loss curves include the losses of ir38 27 , the inductor losses and the losses of the input and output capacitors. the table below shows the inductors used for each of the output voltages in the efficiency measurement. vout (v) lout (h) p/n dcr ( m ?) 1.0 0.82 spm6550t - r82m (tdk) 4.2 1.2 1.0 spm6550t - 1r0m (tdk) 4.7 1.8 1.0 spm6550t - 1r0m (tdk) 4.7 3.3 2.2 7443340220(wurth elektronik) 4.4 5 2.2 7443340220( wurth elektronik) 4.4
ir3827 12 www.irf.com ? 20 13 international rectifier july 18, 2013 typical efficiency a nd power loss curves pv in = 12v, v cc = internal ldo, ldo_select = gnd, i o = 0a - 6a, f s = 600 khz, room temperature, no air flow. note that the efficiency and power loss curves include the losses of ir3827, the inductor losses and the losses of the input and output capacitors. the table below shows the inductors used for each of the output voltages in the efficiency measurement. vout (v) lout (h) p/n dcr ( m ?) 1.0 0.82 spm6550t - r82m (tdk) 4.2 1.2 1.0 spm6550t - 1r0m (tdk) 4.7 1.8 1.0 spm6550t - 1r0m (tdk) 4.7 3.3 2.2 7443340220(wurth elektronik) 4.4 5 2.2 7443340220(wurth elektronik) 4.4
ir3827 13 www.irf.com ? 20 13 international rectifier july 18, 2013 typical efficiency a nd power loss curves pv in = 12v, v cc = external 5v, i o = 0a - 6a, f s = 600 khz, room temperature, no air flow. note that the efficiency and power loss curves include the losses of ir3827, the inductor losses and the losses of the input and output capacitors. the table below shows the inductors used for each of the output v oltages in the efficiency measurement. vout (v) lout (h) p/n dcr ( m ?) 1.0 0.82 spm6550t - r82m (tdk) 4.2 1.2 1.0 spm6550t - 1r0m (tdk) 4.7 1.8 1.0 spm6550t - 1r0m (tdk) 4.7 3.3 2.2 7443340220(wurth elektronik) 4.4 5 2.2 7443340220(wurth elektronik) 4.4
ir3827 14 www.irf.com ? 20 13 international rectifier july 18, 2013 typical efficiency a nd power loss curves pv in = v in = v cc = 5v, i o = 0a - 6a, f s = 600 khz, room temperature, no air flow. note that the efficiency and power loss curves include the losses of ir3827, the inductor losses and the losses of the input and output capacitors. the table below shows the inductors used for each of the output v oltages in the efficiency measurement. vout (v) lout (h) p/n dcr ( m ?) 1.0 0.68 pcmb065t - r68ms (cyntec) 3.9 1.2 0.82 spm6550t - r82m(tdk) 4.2 1.8 0.82 spm6550t - r82m(tdk) 4.7 3.3 1.0 spm6550t - 1r0m(tdk) 4.7
ir3827 15 www.irf.com ? 20 13 international rectifier july 18, 2013 r ds (on ) of mosfets over temp erature at v cc =6.9v r ds (on ) of mosfets over temp erature at v cc =5.1v
ir3827 16 www.irf.com ? 20 13 international rectifier july 18, 2013 typical operating ch aracteristics ( - 40c to +125c)
ir3827 17 www.irf.com ? 20 13 international rectifier july 18, 2013 t ypi cal operating characteristics ( - 40c to + 125c)
ir3827 18 www.irf.com ? 20 13 international rectifier july 18, 2013 theory of operation description the ir382 7 supirbuck tm is a 6 a easy - to - use, fully integrated and highly efficient synchronous buck regulator intended for point - of - load (pol) applications. it includes two ir hexfet s with low r ds(on ) . the bottom fet has an integrated monolithic schottky diode in place of a conventiona l body diode. the ir3827 provides precisely regulated output voltage programmed via two external resistors from 0.6v to 0.86 v in . it uses voltage mode control employing a proprietary pwm modulator with input voltage feedforward . that provides excellent noise immunity , easy loop compensation design, and good line transient response . the ir3827 has a user - selectable internal low dropout (ldo) regulator, allowing single supply operation without resorting to an external bias supply voltage. to further improv e the efficiency, the internal ldo can be bypassed. instead an external bias supply can be used. this feature allows the input bus voltage range extended to 1.0v. the ir382 7 features programmable switching frequency from 300khz to 1. 2 mhz, three selectable soft - start time, and smooth synchronization to an external clock. the other important functions include thermally compensated over current protection, output over voltage protection and thermal shut - down, etc. voltage loop compesn a tion design the ir3827 uses pwm voltage mode control . the output voltage of the pol , sensed by a resistor divider , is fed into an internal error amplifier (e/a). the output of the e/r is then compared to an internal ramp voltage to determine the pulse widt h of the gate signal for the control fet. the amplitude of the ramp voltage is proportional to v in so that the bandwidth of the voltage loop remains almost constant for different input voltages. this feature is called input voltage feedfoward. it allows th e feedback loop design independent of the input voltage. please refer to the next section for more information. a rc network has to be connected between the fb pin and the comp pin to form a feedback compensator. the goal of the compensator design is to achieve a high control bandwidth with a phase margin of 45 or above. the h igh control bandwidth is beneficial for the loop dynamic response, which helps to reduce the number of output capacitors , pcb size and the cost. a phase margin of 45 or higher is desired to ensure the system stability. for most applications, a gain margin of - 10db or higher is preferred to accommodate co mponent variations and to eliminate jittering/noise. the proprietary pwm modulator in ir3827 significantly reduces t he pwm jittering, allowing the control bandwidth in the range of 1/10 th to 1/5 th of the switching frequency. two types of compensators are commonly used: type ii (pi) and type iii (pid), as shown in figure 5 . the selection of the compensation type is dependent on the esr of the output capacitors. electrolytic capacitors have relatively higher esr. if the esr pole is located at the frequency lower than the cross - over fre quency, f c , the esr pole will help to boost the phase margin. thus a type ii compensator can be used. for the output capacitors with low er esr such as ceramic capacitors, type iii compensation is often desired. (a) + - vout r f1 r f2 r c1 c c1 c c2 e/a fb comp r f3 c f3 v ref (b) figure 5 loop compensat or (a) type ii, (b) type iii + - vout r f1 r f2 v ref r c1 c c1 c c2 e/a fb comp
ir3827 19 www.irf.com ? 20 13 international rectifier july 18, 2013 table 1 lists the compensation selection for different types of output capacitors. for more detailed design guideline of voltage loop compensation, please refer to the application note an - 1162, ? compensation design procedure for buck converter with voltage - mode error - amplifier ?. supbuck design tool is also availab le at www.irf.com providing the reference design based on user?s design requirements. t able 1 r ecommended compensation type compensat or location of cross - over frequency type of output capacitors type ii (pi) f lc 5.5v . in this case, th e internal low dropout (ldo) regulator is used. the pwm ramp amplitude (v ramp ) is proportionally changed with v in to maintain the ratio v in /v ramp almost constant throughout v in variation range (as shown in figure 6 ). thus, the control loop bandwidth and phase margin can be maintained constant. feed - forward function can also minimize impact on output voltage from fast v in change. the maximum v in slew rat e is within 1v/s. if an external bias voltage is used as v cc , v in pin should be connected to v cc /ldo_out pin instead of pv in pin. then the feedforward function is disabled. the control loop compensation might need to be adjusted. 0 0 pwm ramp 12v ramp offset 7.3v 12v pwm ramp amplitude = 1.8v pwm ramp amplitude = 2.4v pwm ramp amplitude = 1.095v 16v figure 6 timing diagram for input feedforward under - voltage lockout and por the u nder - v oltage l ockout (uvlo) circuit monitors the voltage of v cc / ldo_output pin and the enable pin . it assures that the mosfet driver outputs remain off whenever either of these two signals is below the set thresholds. normal operation resumes once both v cc / ldo_output and en voltages rise above their thresholds. the por (power on ready) signal is gener ated when all these signals reach the valid logic level (see system block diagram). when the por is asserted , the soft start sequence starts (see soft start section). enable /external pvin monit or the ir3827 has an enable function providing another level of flexibility for start - up. the enable pin has a precise threshold which is internally monitored by under - voltage lockout (uvlo) circuit. if the voltage at enable pin is below its uvlo threshold, both high - side and low - side fets are off . when enabl e pin is below its uvlo, o ver - voltage protection (ovp) is disabled, and pgood stays low.
ir3827 20 www.irf.com ? 20 13 international rectifier july 18, 2013 the enable pin should not be left floating. a pull - down resistor in the range of several kilo ohms is recommended to connect between the enable pin and gnd . in additi on to logical inputs, the enabl e pin can be used to implement precise input voltage uvlo. as shown in figure 7 , the input of the enable pin is derived from the pv in voltage by a set of resistive divider , r1 and r2 . by selecting different divider ratios, users can program the uvlo threshold voltage. th e bus voltage uvlo is a very desirable feature. it prevent s the ir3827 from regulating at pv i n lower than the desired voltage level . figure 8 shows the start - up waveform with the input uvlo voltage set at 10v. ir3827 enable vin r1 r2 figure 7 implementation of input under - voltage lockout (uvlo) using enable pin enable threshold voltage1.2v pvin (12v) vcc enable intl_ss vout 10v figure 8 illustration of start - up with pvin uvlo threshold voltage of 10v. the i nternal soft - start is used in this case. user selectable internal ldo the ir3827 has an internal low dropout regulator (ldo), offering two ldo voltage options ? 5.1v and 6.9v. 5.1v v cc voltage results in higher light load efficiency due to the lower gate charge loss , while 6.9 v cc voltage results in higher full load efficiency due to less conduction loss. user can select the desired v cc voltage based on the design target. the selection of the ldo voltage is achieved with ldo_select pin, as shown in table 2 . it should be noted that 6.9v v cc voltage results in faster switching speed and may cause higher voltage spike at the sw node than 5.1v v cc voltage. t able 2 c onfiguration of inte rnal ldo ldo_select vcc/ldo_out float 5.1v gnd 6.9v the internal ldo is beneficial for single rail (supply) applications, where no external bias supplies will be needed. for these applications, v in pin should be connected to pv in and v cc /ldo_out pin is left floating as shown in figure 9 . 1.0 f and 2.2 f ceramic bypass capacitors should be placed close to v in pin and v cc / ldo_out pin respectively. ir3827 vcc/ ldo_out pgnd vin pvin 1.0uf 2.2uf input =5v-21v figure 9 internally biased single - rail configuration when v in drops below 5.5v (ldo_select = float), or 7.3v (ldo_select = gnd), the internal ldo enters the dropout mode. figure 10 shows the v cc /ldo_out voltage for v in =pv in =5v with switching frequency of 600khz and 1200khz respectively. alternatively, if the input bus voltage, pv in , is in the range of 4.5v to 7.5v, v cc / ldo_out pin can be
ir3827 21 www.irf.com ? 20 13 international rectifier july 18, 2013 directly connected to the pv in pin to bypass the internal ldo and therefore to avoid the voltage drop on the internal ldo. this configuration is illustrated in figure 11 . figure 12 shows the configuration using an external v cc voltage. with this configuration, the input voltage range can be extended down to 1.0v. please note that the input feedforward function is disabled for this configuration. the feedback compensation needs to be adjusted accordingly. it should be noted as the v cc voltage decreases , the efficiency and the over current limit will decrease due to the increase of r ds(on) . please refer to the section of the over current protection for more information. figure 10 ldo dropout voltage at v in =pv in =5v ir3827 vcc/ ldo_out pgnd input =4.5v-7.5v vin pvin 1.0uf 2.2uf figure 11 single - rail configuration for 4.5v - 7v inputs ext vcc 4.5v-7.5v ir3827 vcc/ ldo_out pgnd vin pvin 2.2uf input =1.0v-21v figure 12 use external bias voltage . soft - start the ir3827 has an internal digital soft - start circuit to control the output voltage rise time, and to limit the current surge at the start - up. to ensure correct start - up, the soft - start sequence initiates when the enable and vcc voltages rise above their uvlo thresholds and generate the power on ready (por) signal. the slew rate of the internal soft - start can be adjusted externally with ss_select pin, as shown in table 3 . table 3 user selectable soft - start time ss_select slew rate (mv/ s) soft - start time ( ms ) vcc 0.4 1.5 float 0.2 3 gnd 0.1 6 figure 13 shows the waveforms dur ing the soft start. the corresponding soft - start time can be calculated as follows. slewrate v v t ss 15 . 0 75 . 0 ? = it should be noted that during the soft - start the over - current protection (ocp) and over - voltage protection (ovp) is enabled to protect the device for any short circuit or over voltage condition.
ir3827 22 www.irf.com ? 20 13 international rectifier july 18, 2013 por intl_ss vout 0.15v 0.75v t 1 t 2 t 3 1.5v 3.0v figure 13 theoretical start - up waveforms using internal soft - start power up sequencing the ir3827 provides the simultaneous or ratiometric sequencing function with seq pin. as shown in the block diagram, the error - amplifier (e/a) has three positive inputs. t he input with the lowest voltage is used for regulating the outp ut voltage and the other two inputs are ignored. in practice , the voltage of the other two inputs should be about 200mv greater than the low - voltage input so that their effects can completely be ignored. seq pin is internally biased to 3.3v via a high impe dance path. for normal o peration, seq pin is left floating. in sequencing operation , the voltage at seq pin, v seq , should be kept to zero until the internal soft - start is finished. then v seq is ramped up and the feedback voltage, v fb , follows v seq . when v seq is above 0. 6 v , the e rror - a mplifier switches to v ref and v fb starts to follow v ref . the final v seq voltage after sequencing startup should be between 0.7v ~ 3.3v. figure 14 shows the typical application circuit for sequencing operation. v seq is derived from the output of another voltage regulator (master) through a resistor divider composed of r e and r f . if the ratio of this resistor divider is equal to that of the feedback resistor divider i.e. r e /r f =r c /r d , simultaneous start - up is achieved. that is, the output voltage of the slave follows that of the master until the voltage at the seq pin of the slave reaches 0. 6 v. after v seq of the slave exceeds 0. 6 v, the internal 0.6v reference voltage of the slave dicta tes its output. to achieve ratiometric operation, r e /r f > r c /r d should be used. table 4 summarizes the configurations to achieve simultaneous/ratiometric sequencing operations and normal start - up using the internal soft - start . figure 15 show s the typical waveforms for sequencing operations. boot vcc/ ldo _out fb comp gnd pgnd sw pgood rt/sync pvin vin enable ir3827 ss _select vin pgood ldo _select seq r e r f v o1 (master ) r c r d figure 14 application circuit for simultaneous and ratiometric sequencing operation table 4 start - up configurations operating mode v seq configuration internal soft - start floating D simultaneous sequencing ramp up from 0v r e /r f =r c /r d ratiometric sequencing ramp up from 0v r e /r f >r c /r d vcc v ref =0.6v 1.2v soft start (slave) enable (slave) vo1 (master) vo2 (slave) (a) vo1 (master) vo2 (slave) (b) figure 15 typical waveforms for sequencing operation: (a) s imultaneous; (b) r atiometric pre - bias start -up ir3827 is able to start up into a pre - charged output smoothly , which prevents oscillation s and disturbances of the output voltage.
ir3827 23 www.irf.com ? 20 13 international rectifier july 18, 2013 the output starts in an as ynchronous fashion and keeps the synchronous mosfet (sync fet) off until the first gate signal for control mosfet (ctrl fet) is generated. figure 16 shows a typical pre - bias condition at start up. the gate signal of the control fet is determined by the loop compensator. the sync fet always starts with a narrow pulse width (12.5% of a switching period) and gradually increases its duty cycle with a step of 12.5% until it reaches the steady state value . the number of these startup pulses for each step is 16 and it?s internally programmed. figure 17 shows the series of 16x8 startup pulses. it should be noted that pgood is not active until the first gate signal for co ntrol fet is generated. please refer to power good section for more information. v o pre-bias voltage t figure 16 pre - bias start - up ... ... ... hdrv ... ... ... 16 end of pb ldrv 12. 5 % 25% 87. 5% 16 ... ... ... ... figure 17 pre - bias startup pulses shutdown ir3827 can be shut down by pulling the enable pin below its 1.0v threshold. b oth the high side and the low side driver s are pulled low . operating frequency the switching frequency can be programmed between 300khz ? 1 2 00khz by connecting an exter nal resistor from rt pin to gnd. rt can be calculated as follows. 953 . 0 19954 ? = t s r f where f s is in khz, and rt is in k ? . table 5 shows the different oscillator frequency and its corresponding rt for easy reference. table 5 switching frequency vs. r t r t ( k ? f s ( k hz) 80.6 300 60.4 400 48.7 500 39.2 600 34 700 29.4 800 26.1 900 23.2 1000 21 1100 19.1 1200 over current protect ion the over current (oc) protection is performed by sensing current through the r ds(on) of the synchronous mosfet. this method enhances the converter?s efficiency, reduces cost by eliminating a current sense resistor and any layout related noise issues. the c urrent limit is pre - set internally and is compensated according to the ic temperature. so at different ambient temperature, the over - current trip threshold remains almost constant. detailed operation of ocp is explained as follows. over current protection circuit senses the inductor current flowing through the synchronous mosfet closer to the valley point. ocp circuit samples this current for 40nsec typically after the rising edge of the pwm set pulse which has a width of 12.5% of the switching p eriod. the pwm pulse starts at the falling edge of the pwm set pulse. this makes valley current sense more robust as current is sensed close to the bottom of the inductor downward slope where transient and switching noise are lower and helps to prevent fal se tripping due to noise and transient. an oc condition is detected if the load current exceeds the threshold, the converter enters into hiccup mode. pgood will go low and the internal
ir3827 24 www.irf.com ? 20 13 international rectifier july 18, 2013 soft start signal will be pulled low. the converter goes into hiccup mo de with some hiccup blanking time as shown in figure 18 . the convertor stays in this mode until the over load or short circuit is removed. with differe nt ss_select configurations, the hiccup blanking time is different. please refer to the electrical table for details. the actual dc output current limit point will be greater than the valley point by an amount equal to approximately half of peak to peak in ductor ripple current. 2 i i i limit ocp ? + = i ocp = dc current limit hiccup point i limit = over current limit ( valley of inductor current) i= peak - to - peak i nductor ripple current hdrv ldrv pgood 0 il 0 over current limit 0 ... ... 0 hiccup blanking time figure 18 timing diagram for hiccup o ver current protection o ver current limit is affected by the v cc voltage. for some single rail operations where v in is 5v or less, the ocp limit will de - rated due to the drop of v cc voltage. figure 19 and figure 20 show the over current limit for two single rail applications with v in =pv in =5v and v in =pv in =v cc =4.5v respectively. figure 19 ocp limit at v in =pv in =5v using internal ldo figure 20 ocp limit at v in =pv in =v cc =4.5v over - voltage protection ( ovp) over - voltage protection in ir3827 is achieved by comparing fb pin voltage to a pre - set threshold. ovp threshold is set at 1.2 vref. when fb pin voltage exceeds the over voltage threshold, an over voltage trip signal asserts after 2us (typ.) delay. then the high side drive signal hdrv is turned off immediately, pgood flags low. the sync fet remains on to discharge the output capac itor. when the v fb voltage drops below the threshold, the sync fet turns off to prevent the complete depletion of the output capacitor. after that, hdrv remains off until a reset is performed by cycling either v cc or enable. figure 21 shows the timing diagram for over voltage protection. please note that ovp comparat or becomes active only when the ir3827 is enabled . power good output ir3827 continually monitors the output voltage via fb voltage. the fb voltage is an input to the window comparator with upper and lower threshold of 120% and 85% of the reference voltage respectively. pgood signal is high whenever fb voltage is within the pgood comparator window thresholds. for pre - biased start - up, pgood is not active until the first gate signal of the control fet is generated. the pgood pin is open drain and it needs to be externally pulled high. high state indicates that output is in reg ulation. in addition, pgood is also gated by other faults including over current and over temperature. when
ir3827 25 www.irf.com ? 20 13 international rectifier july 18, 2013 either of the faults occurs, pgood pin will be pulled low. hdrv 0 0 0 ldrv fb 1.2*vref 0 pgood 0.6v figure 21 timing diagram for o ver voltage protection thermal shutdown temperature sensing is provided inside ir3827. the trip threshold is typically set to 145 o c. when trip threshold is exceeded, thermal shutdown turns off both mosfets and resets the internal soft start. automatic re start is initiated when the sensed temperature drops within the operating range. there is a 20 c hysteresis in the thermal shutdown threshold. external synchroniza tion ir3827 incorporates an internal phase lock loop (pll) circuit which enables synchronizat ion of the internal oscillator to an external clock. this function is important to avoid sub - harmonic oscillations due to beat frequency for embedded systems when multiple point - of - load (pol) regulators are used. a multi - function pin, rt/sync, is used to c onnect the external clock. if the external clock is present before the converter turns on, rt/sync pin can be connected to the external clock signal solely and no other resistor is needed. if the external clock is applied after the converter turns on, or t he converter switching frequency needs to toggle between the external clock frequency and the internal free - running frequency, an external resistor from rt/sync pin to gnd is required to set the free - running frequency. when an external clock is applied to rt/sync pin after the converter runs in steady state with its free - running frequency, a transition from the free - running frequency to the external clock frequency will happen. this transition is to gradually make the actual switching frequency equal to th e external clock frequency, no matter which one is higher. on the contrary, when the external clock signal is removed from rt/sync pin, the switching frequency is also changed to free - running gradually. in order to minimize the impact from these transition s to output voltage, a diode is recommended to add between the external clock and rt/sync pin , as shown in figure 22. figure 23 shows the timing diagram of t hese transitions. an internal compensation cir cuit is used to change the pwm ramp slope according to the clock frequency applied on rt/sync pin. thus, the effective amplitude of the pwm ramp (v ramp ), which is used in compensation loop calculation, has minor impact from the variation of the external sy nchronization signal. ir 3827 rt/sync gnd figure 22 configuration of external s ynchronization sw sync ... ... gradually change fs 1 fs 2 fs 1 free running frequency synchronize to the external clock return to free - running freq gradually change figure 23 timing diagram for synchronization to the e xternal c lock (fs1 < fs2 or fs1 > fs2)
ir3827 26 www.irf.com ? 20 13 international rectifier july 18, 2013 minimum on time cons iderations the minimum on time is the shortest amount of time for which ctrl fet may be reliably turned on, and this depends on the internal timing delays. for ir3827, the worst case minimum on - time is specified as 60 ns. any design or application using ir3827 must ensure operation with a pulse width that is higher than this minimum on - tim e and preferably higher than 60 ns. this is necessary for the circuit to operate without jitter and pulse - skipping, which can cause high inductor current ripple and high output volt age ripple. s in out s on f v v f d t = = in any application that uses ir3827, the following condition must be satisfied: on on t t (min) s in out on f v v t (min) , therefore, (min) on out s in t v f v the minimum output voltage is limited by the reference voltage and hence v out(min) = 0.6 v. therefore, therefore, at the maximum recommended input voltage 21v and minimum output voltage, the co nverter should be designed at a switching frequency that does not exceed 476 khz. conversely, for operation at the maximum recommended operating frequency (1. 32 mhz) and minimum output voltage (0.6v). the input voltage (pv in ) should not exceed 7.57v , other wise pulse skipping will happen. maximum duty ratio a certain off - time is specified for ir3827. this provides an upper limit on the operating duty ratio at any given switching frequency. the off - time remains at a relatively fixed ratio to switching period in low and mid frequency range, while in high frequency range this ratio increases, thus the lower the maximum duty ratio at which ir3827 can operate. figure 24 shows a plot of the maximum duty ratio vs. the switching frequency. figure 24 maximum duty cycle vs. switching frequency. s v t v f v on out s in / 10 ns 60 v 6 . 0 (min) (min) = =
ir3827 27 www.irf.com ? 20 13 international rectifier july 18, 2013 design example the following example is a typical application for ir3827. the application circuit is shown in figure 28 . pv in = v in = 12v ( 10%) v o = 1.2v i o = 6a peak - to - peak ripple voltage = 1% of v o v o = 4% of v o (for 30% load trans ient) f s = 600 khz external pvin monito r (input uvlo) as explained in the section of enable/external pv in monitor , the input voltage, pv in , can be monitored by connecting the enable pin to pv in through a set of resistor divider . when pv in exceeds the desired voltage level such that the voltage at the enable pin exceeds the enable threshold, 1.2v, the ir3827 is turned on. the implementation of this function is shown in figure 7 . for a typical enable threshold of v en = 1.2 v 2 . 1 2 1 2 (min) = = + en in v r r r pv en in en v pv v r r ? = (min) 1 2 for the minimum input voltage p v in (min) = 9.2v, sel ect r 1 =49.9k?, and r 2 =7.5k? . switching frequency for f s = 600 khz, select r t = 39.2 k , from table 5 . output voltage setting output voltage is set by the reference voltage and the external voltage divider connected to the fb pin. the fb pin is the inverting input of the error amplifier, whi ch is internally referenced to 0.6v. the divider ratio is set to provide 0.6v at the fb pin when the output is at its desired value. the output voltage is defined by using the following equation: ) 1 ( 2 1 f f ref o r r v v + = r f1 and r f2 are the feedback resistor divider, as shown in figure 25 . for the selection of r f1 and r f2 , please see feedback compensation section. ir3827 fb vout r f1 r f2 figure 25 the output voltage is programmed through a set of feedback resistor divider bootstrap capacitor selection to drive the control fet, it is necessary to supply a gate voltage at least 4v greate r than the voltage at the sw pin, which is connected to the source of the control fet. this is achieved by using a bootstrap configuration, which comprises the internal bootstrap diode and a n external bootstrap capacitor, c1 , as shown in figure 26 . the operation of the circuit is as follows: when the sync fet is turned on, the capacitor node connected to sw is pulled low . v cc starts to charge c1 through the internal bootstrap didoe. the voltage , v c , acro ss the bootstrap capacitor c1 can be calculated as d cc c v v v ? = w here v d is the forward voltage drop of the bootstrap diode. when the control fet turns on in the next cycle, the sw node voltage rises to the bus voltage , pv in . the voltage at the boot pin becomes: d cc in boot v v pv v ? + = a good quality ceramic capacitor of 0.1 ? f with voltage rating of at least 25v is recommended for most applications.
ir3827 28 www.irf.com ? 20 13 international rectifier july 18, 2013 l v c c 1 v in v cc sw + - boot pgnd + v d - cvin figure 26 bootstrap circuit to generate the supply voltage for the high - side driver voltage input capacitor sele ction good quality input capacitor s are necessary to minimize the input ripple voltage and to supply the switch current during the on - time. the input capacitors should be selected based on the rms value of the input ripple current and requirement of the input ripple voltage. the rms valu e of the input ripple current can be calculated as follows: ) 1 ( d d i i o rms ? = where d is the duty cycle and i o is the output current. for i o = 6 a and d=0.1, i rms = 1.8a the input voltage ripple is the result of the charging of the input capacitors and t he voltage induced by esr and esl of the input capacitors. ceramic capacitors are recommended due to their high ripple current capabilities. they also feature low esr and esl at higher frequency which enables better efficiency. for this application, it is suggested to use three 10 f/25v ceramic capacitors, c3216x5r1e106m , from tdk. in addition, although not mandatory, a 1x330uf, 25v smd capacitor eev - fk1e331p from panasonic may also be used as a bulk capacitor and is recommended if the input power supply is not located close to the converter. inductor selection the inductor is selected based on output power, operating frequency and efficiency requirements. a low inductor value causes large ripple current, resulting in the smalle r size, faster response to a load transient but poor efficiency and high output noise. generally, the selection of the inductor value can be reduced to the desired maximum ripple current in the inductor ( ? i). the optimum point is usually found between 20% and 50% ripple of the output current. the saturation current of the inductor is desired to be higher than the over current limit plus the inductor ripple current. an inductor with soft - saturation characteristic is recommended. for the buck converter, the inductor value for the desired operating ripple current can be determined using the following relation: t i l v pv l o in ? ? = ? max max ; s f d t = ? s l in o o in f i v v v pv l ? ? = max max ) ( where: p v in max = maximum input voltage v 0 = output voltage ?l l max = maximum inductor peak - to - peak ripple current f s = switching frequency ?w = on time d = duty cycle select ?l l max i o , then the output inductor is calculated to be 1.0 h. select l =1.0 h, spm6550t - 1r0m, from tdk which provides a compact, low profile inductor suitable for this application. output capacitor sel ection output capacitors are usually selected to meet two specific requirements: (1) output ripple voltage and (2) load transient response. the load transient response is also greatly affected by the cont rol bandwidth. so it is common practice to select the output capacitors to meet the requirements of the
ir3827 29 www.irf.com ? 20 13 international rectifier july 18, 2013 output ripple voltage first , and then design the control bandwidth to meet the transient load response. for some cases, even with the highest allowable control bandwidth, the resulting load transient response still cannot meet the requirement. the number of output capacitors then need to be increased. the voltage ripple is attributed by the ripple current charging the output capacitors, and the voltage d rop due to the equivalent series resistance (esr) and the equivalent series inductance (esl . following lists the respective peak - to - peak ripple voltages: esl l v pv v esr i v f c i v o in esl o l esr o s o l c o ? = ? ? = ? ? = ? ) ( 8 ) ( max ) ( max ) ( where i l max is m aximum i nductor peak - to - peak r ipple c urrent . good quality ceramic capacitors are recommended due to their low esr , esl and the small package size. it should be noted that the capacitance of ceramic capacitors are usually de - rated with the dc and ac biased voltage. it is important to use the de - rated capacitance value for the calculation of output ripple voltage as well as the voltage loop compensation design. the de - rated capacitance value may be obtained from the manufacturer?s datasheets. in this case, t hree 22uf ceramic capacitors, c2012x5r0j226m , from tdk ar e used to achieve 12mv peak - to - peak ripple voltage requirement . the de- rated capacitance value with 1.2vdc bias and 10mvac voltage is around 18 uf each. feedback compensatio n for this design, t he resonant frequency of the output lc filter , f lc , is khz 6 . 21 10 18 3 10 0 . 1 2 1 2 1 6 6 = = = ? ? o o lc c l f the equivalent esr zero of the output capacitor s, f esr , is. khz 10 95 . 2 10 18 10 3 2 1 3 3 2 1 3 6 3 = = = ? ? o esr c esr f select crossover frequency f 0 =100 khz according to table 1 , type iii b compensation is selected for f lc ir3827 30 www.irf.com ? 20 13 international rectifier july 18, 2013 1 1 1 2 1 c c z c r f = ) ( 2 1 1 3 3 2 f f f z r r c f + = 0 1 = p f 3 3 2 2 1 f f p c r f = 2 1 3 2 1 c c p c r f = f z2 and f p2 are selected to achieve phase boost ? =70 o. khz 6 . 17 70 sin 1 70 sin 1 10 100 sin 1 sin 1 3 0 2 = + ? = + ? = f f z khz 568 70 sin 1 70 sin 1 10 100 sin 1 sin 1 3 0 2 = ? + = ? + = f f p f z1 is selected to provide extra phase boost . khz 8 . 8 2 / 2 1 = = z z f f f p3 is set at one half of the switching frequency to damp the switching noise. khz 300 2 / 3 = = s p f f the selected compensation parameters are: r f1 =3.32k ? , r f2 =3.32k ?, r f3 =100?, c f3 =2200pf, r c1 =2k?, c c1 =10nf, c c2 =180pf.
ir3827 31 www.irf.com ? 20 12 international rectifier july 18 , 2013 application diagram boot vcc/ldo _out fb comp gnd pgnd sw pgood rt/sync pvin vin enable ir3827 ss _select 12v pgood 1.2v ldo _select seq 1.0uf 3x10uf c in c 32 49.9k r 18 7.5k r 19 49.9k r 17 2.2uf c 23 39.2k r 9 0.1uf c 24 0.1uf c 7 l 1 1.0uh 3.32k r 2 100 ? r 4 3.32k r 3 2.0k r 1 c 26 10nf c 11 180 pf c 8 2200 pf cout 3x22uf c 14 0.1uf figure 28 single rail 6a pol application circuit: pv in =v in =12v, v o =1.2v, io=6a, f sw =600khz s uggested bill of materials qty part reference value description manufacturer part number 3 c in 10uf 1206, 25v, x5r, 20% tdk c3216x5r1e106m 3 c7 c14 c24 0.1uf 0603, 25v, x7r, 10% murata grm188r71e104ka01b 1 c8 2200pf 0603,50v,x7r murata grm188r71h222ka01b 1 c11 180pf 0603, 50v, np0, 5% murata grm1885c1h181ja01d 3 c out 22uf 0805, 6.3v, x5r, 20% tdk c2012x5r0j226m 1 c23 2.2uf 0603, 16v, x5r, 20% tdk c1608x5r1c225m 1 c26 10nf 0603, 25v, x7r, 10% murata grm188r71e103ka01j 1 c32 1.0uf 0603, 25v, x5r, 10% murata grm188r61e105ka12d 1 l1 1.0uh smd 7.1x6.5x5mm,4.7m tdk spm6550t - 1r0 1 r1 2k thick film, 0603,1/10w,1% panasonic erj - 3ekf2001v 2 r2,r3 3.32k thick film, 0603,1/10w,1% panasonic erj - 3ekf3321v 1 r4 100 thick film, 0603,1/10w,1% panasonic erj - 3ekf1000v 1 r9 39.2k thick film, 0603,1/10w,1% panasonic erj - 3ekf3922v 2 r17 r18 49.9k thick film, 0603,1/10w,1% panasonic erj - 3ekf4992v 1 r19 7.5k thick film, 0603,1/10w,1% panasonic erj - 3ekf7501v 1 u1 ir3827 pqfn 4x5mm ir ir3827mpbf
ir3827 32 www.irf.com ? 20 12 international rectifier july 18 , 2013 application diagram boot vcc/ldo _out fb comp gnd pgnd sw pgood rt/sync pvin vin enable ir3827 ss _select 12v pgood 1.2v ldo _select seq 1.0uf 3x10uf c in c 32 49.9k r 18 7.5k r 19 49.9k r 17 2.2uf c 23 39.2k r 9 0.1uf c 24 0.1uf c 7 l 1 1.0uh 3.32k r 2 100 ? r 4 3.32k r 3 806 ? r 1 c 26 22nf c 11 180 pf c 8 2200 pf cout 3x22uf c 14 0.1uf ext vcc=5v figure 29 6a pol application circuit with external 5v v cc : pv in =v in =12v, v o =1.2v, io=6a, f sw =600khz . please note that loop compensation is adjusted to consider the absence of the input voltage feedforward. 1v boot vcc/ldo _out fb comp gnd pgnd sw pgood rt/sync pvin vin enable ir3827 ss _select 5v pgood ldo _select seq 1.0uf 4x10uf c in c 32 enable 49.9k r 17 2.2uf c 23 39.2k r 9 0.1uf c 24 0.1uf c 7 l 1 0.68uh 3.32k r 2 100 ? r 4 4.99k r 3 2k r 1 c 26 4.7nf c 11 100 pf c 8 2200 pf cout 4x22uf c 14 0.1uf figure 30 single rail 6a pol application circuit: pv in =v in =5v, v o =1.0v, io=6a, f sw =600khz
ir3827 33 www.irf.com ? 20 13 international rectifier july 18, 2013 typical operating wa veforms v in = 12v, v 0 = 1.2 v, i 0 = 0 - 6 a, unless otherwise specified, ldo_select = float. room temperature, no air flow figure 31 start up at 6a load wi th ss_select pin figure 32 start up at 6a load with ss_select pin f loating . ch 1 :v in , ch 2 :enable, ch 3 :v o ,ch 4 : p good floating . ch 1 :v in , ch 2 :enable, ch 3 :v o ,ch 4 :v cc figure 33 start up with 1.06v pre bias , 0a load figure 34 output voltage ripple, 6a load ch 2 : v out ch 3 : v o , ch 4 : p good figure 35 inductor node at 6a load, figure 36 short circuit (hiccup) recovery, ldo_select = float ch3:lx ss_select = float , ch3:vout , ch4:iout
ir3827 34 www.irf.com ? 20 13 international rectifier july 18, 2013 typical operating wa veforms v in = 12v, v 0 = 1.2 v, i 0 = 0 - 6 a, unless otherwise specified, ldo_select = float. room temperature, no air flow figure 37 transient response, 4.2a to 6a figure 38 feed forward for v in change step load ch 2 :v out ch4 -i out from 6.8 to 15v and back to 6.8v . ch 2 -v out , ch 4 -v in figure 39 bode plot at 6a load, bandwidth = 105 khz , and phase margin = 5 3 degrees and gain margin = -1 2 db
ir3827 35 www.irf.com ? 20 13 international rectifier july 18, 2013 typical operating wa veforms v in = 12v, v 0 = 1.2 v, i 0 = 0 - 6 a, unless otherwise specified, ldo_select = float. room temperature, no air flow figure 40 efficiency vs. load current, ldo_select = gnd and float figure 41 power loss vs. load current, ldo_select = g nd and float
ir3827 36 www.irf.com ? 20 13 international rectifier july 18, 2013 typical operating wa veforms v in = 12v, v 0 = 1.2 v, i 0 = 0 - 6 a, unless otherwise specified, ldo_select = float. room temperature, no air flow figure 42 thermal image of the board at 6a load, ldo_select= float (vcc=5.1v) ir3827=70c, inductor=40c figure 43 thermal image of the board at 6a load, ldo_select= gnd (vcc=6.9v) ir3827=60c, inductor=38c
ir3827 37 www.irf.com ? 20 13 international rectifier july 18, 2013 layout recommendatio ns the layout is very important when designing high frequency switching converters. layout will affect noise pickup and can cause a good design to perform with worse than expected results. make the connections for the power components in the top layer with wi de, copper filled areas or polygons. in general, it is desirable to make proper use of power planes and polygons for power distribution and heat dissipation. the inductor, output capacitors and the ir38 2 7 should be as close to each other as possible. this helps to reduce the emi radiated by the power traces due to the high switching currents through them. place the input capacitor directly at the pv in pin of ir 382 7. the feedback part of the system should be kept away from the inductor and other noise sourc es. the critical bypass components such as capacitors for v in and v cc should be close to their respective pins. it is important to place the feedback components including feedback resistors and compensation components close to fb and comp pins. in a multil ayer pcb use one layer as a power ground plane and have a control circuit ground (analog ground), to which all signals are referenced. the goal is to localize the high current path to a separate loop that does not interfere with the more sensitive analog c ontrol function. these two grounds must be connected together on the pc board layout at a single point. it is recommended to place all the compensation parts over the analog ground plane in top layer. the power qfn is a thermally enhanced package. based o n thermal performance it is recommended to use at least a 4 - layers pcb. to effectively remove heat from the device the exposed pad should be connected to the ground plane using via holes. figure 44 - figure 47 illustrates the implementation of the layout guidelines outlined above, on the irdc38 2 7 4 - layer demo board. figure 44 irdc3827 demo board ? top layer pv in p gnd agnd vout compensation parts should be placed as close as possible to the comp pin resistor rt should be placed as close as possible to their pins enough copper & minimum ground length path between input and output sw node copper is kept only at the top layer to minimize the switching noise all bypass caps should be placed as close as possible to their connecting pins
ir3827 38 www.irf.com ? 20 13 international rectifier july 18, 2013 figure 45 irdc3827 demo board ? bottom layer figure 46 irdc3827 demo board ? middle layer 1 pv in p gnd vout single point connection between agnd & pgnd, should be close to the supirbuck kept away from noise sources agnd feedback and vsns trace routing should be kept away from noise sources p gnd
ir3827 39 www.irf.com ? 20 13 international rectifier july 18, 2013 figure 47 irdc3827 demo board ? middle layer 2 p gnd
ir3827 40 www.irf.com ? 20 13 international rectifier july 18, 2013 pcb metal and compon ent placement evaluations have shown that the best overall performance is achieved using the substrate/pcb layout as shown in following figures. pqfn devices should be placed to an accuracy of 0.050mm on both x and y axes. self - centering behavior is highly dependent on solders a nd processes, and experiments should be run to confirm the limits of self - centering on specific processes. for further information, please refer to ?supirbuck ? multi - chip module (mcm) power quad flat no - lead (pqfn) board mounting application not e.? (an1132) figure 48 pcb metal pad spacing (all dimensions in mm) * contact international rectifier to receive an electronic pcb library file in your preferred format
ir3827 41 www.irf.com ? 20 13 international rectifier july 18, 2013 solder resist ir recommends that the larger power or land area pads are solder mask defined (smd.) this allows the underlying copper traces to be as large as possible, which helps in terms of current carrying capability and device cooling capability. when using smd pads, the underlying copper traces should be at least 0.05mm larger (on each edge) than the solder mask window, in order to accommodate any layer to layer misalignment. (i.e. 0.1mm in x & y.) however, for the smaller signal type leads around the edge of the device, ir recommends that these are non solder mask defined (nsmd) or copper defined. when using nsmd pads, the solder resist window should be larger than the copper pad by at least 0.025mm on each edge, (i.e. 0.05mm in x&y,) in order to accom modate any layer to layer misalignment. ensure that the solder resist in - between the smaller signal lead areas are at least 0.15mm wide, due to the high x/y aspect ratio of the solder mask strip. figure 49 solder resist
ir3827 42 www.irf.com ? 20 13 international rectifier july 18, 2013 stencil design stencils for pqfn can be used with thicknesses of 0.100 - 0.250mm (0.004 - 0.010"). stencils thinner than 0.100mm are unsuitable because they deposit insufficient solder paste to make good solder joints with the ground pad; high reductions sometimes create sim ilar problems. stencils in the range of 0.125mm - 0.200mm (0.005 - 0.008"), with suitable reductions, give the best results. evaluations have shown that the best overall performance is achieved using the stencil design shown in following figure. this design i s for a stencil thickness of 0.127mm (0.005"). the reduction should be adjusted for stencils of other thicknesses. figure 50 stencil pad spacing (all dimensions in mm)
ir3827 43 www.irf.com ? 20 13 international rectifier july 18, 2013 marking information package inform ation
ir3827 44 www.irf.com ? 20 13 international rectifier july 18, 2013 environmental qualif ications qualification level industrial moisture sensitivity level 4mm x 5mm pqfn jedec level 2 @ 260c esd machine model (jesd22 - a115a) class b 200v to <400v human body model (jesd22 - a114f) class 2 2000v to < 4000v charged device model (jesd22 - c101d) class iii 500v to 1000v rohs 6 compliant yes ? qualification standards can be found at international rectifier web site: http://www.irf.com ?? exceptions to aec - q101 requirements are noted in the qualification report. data and specifications subject to change without notice. qualification standards can be found on irs web site. ir world headquarters: 233 kansas st., el segundo, california 90245, usa tel: (310) 252 - 7105 tac fax: (310) 252 - 7903 visit us at www.irf.com for sales contact information . www.irf.com

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